16.2 Virtual Address Space
Kernel mode virtual address space is divided into regions differentiated by the high-order bits of the virtual address, as shown in Figure 16-3.
Figure 16-3 Kernel Mode Address Space
References to kseg1 are not mapped through the TLB; the physical address is selected by subtracting 0xA000 0000 from the virtual address.
Caches are disabled for accesses to these addresses, and physical memory (or memory-mapped I/O device registers) are accessed directly.
References to ksseg are mapped through the TLB.
References to kseg3 are mapped through the TLB.
References to this space are not mapped; the physical address selected is taken directly from bits 39:0 of the virtual address. Bits 61:59 of the virtual address specify the cache algorithm, described in Chapter 4, the section titled "Cache Algorithms." If the cache algorithm is either uncached or uncached accelerated (values of 2 or 7) the space contains four physical pages; access to addresses whose bits 56:40 are not equal to 0 cause an Address Error exception. Address bits 58:57 carry the uncached attribute (described in Chapter 6, the section titled "Support for Uncached Attribute"), and are not checked for address errors.
If the cache algorithm is neither uncached nor uncached accelerated, the space contains a single physical page, as on the R4400 processor. In this case, access to addresses whose bits 58:40 are not equal to a zero cause an Address Error exception, as shown in Figure 16-4.
Figure 16-4 xkphys Virtual Address Space